Hybrid Real-Time Frame and Bit Synchronization for Mixed Signal Data Acquisition System
This paper presents the design and successful implementation of a hybrid real-time telemetry receiver system based on BPSK demodulation, bit synchronization, and frame synchronization implemented on a Field-Programmable Gate Array (FPGA). The general aim is to eliminate the constraints of traditional analog implementations complexity, size, and tunability by leveraging the FPGA's parallel processing and hardware optimization capabilities. The system introduces novelty by jointly digitalizing various essential elements: a Costas loop with a Digital Controlled Oscillator (DCO) for robust carrier recovery, a timing recovery circuit with the Early-Late Gate algorithm to synchronize bits, and a frame synchronizer with cross-correlation. Moreover, we use 32-bit validation with the Fletcher checksum algorithm to ensure high data integrity and identify transmission errors or corruption. The system can have a flexible range of bit rates from 1 kbps to 64 kbps, with a carrier frequency of 1 MHz and a message signal frequency of 512 kHz. The results indicate that the complete telemetry receiver with a BPSK demodulator has been fully implemented on the Xilinx Virtex UltraScale+. This digital design produces size complexity reduction and better tunability than an analog design. The suggested solution offers real-time performance and superior flexibility in timing for synchronizing and checking data integrity, significantly improving the overall reliability of data receipt and processing in telemetry applications.